Hardware spiking neural network prototyping and ap

Authors: Seamus Cawley Fearghal Morgan Brian McGinley Sandeep Pande Liam McDaid Snaider Carrillo Jim Harkin

Publish Date: 2011/04/02

Volume: 12, Issue: 3, Pages: 257-280

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Abstract

EMBRACE has been proposed as a scalable reconfigurable mixed signal embedded hardware Spiking Neural Network SNN device EMBRACE which is yet to be realised targets the issues of area power and scalability through the use of a low area low power analogue neuron/synapse cell and a digital packetbased Network on Chip NoC communication architecture The paper describes the implementation and testing of EMBRACEFPGA an FPGAbased hardware SNN prototype The operation of the NoC interneuron communication approach and its ability to support large scale reconfigurable highly interconnected SNNs is illustrated The paper describes an integrated training and configuration platform and an onchip fitness function which supports GAbased evolution of SNN parameters The practicalities of using the SNN development platform and SNN configuration toolset are described The paper considers the impact of latency jitter noise introduced by the NoC router and the EMBRACEFPGA processorbased neuron/synapse model on SNN accuracy and evolution time Benchmark SNN applications are described and results demonstrate the evolution of high quality and robust solutions in the presence of noise The reconfigurable EMBRACE architecture enables future investigation of adaptive hardware applications and self repair in evolvable hardwareThis research is supported by Science Foundation Ireland under Grant No 07/SRC/I1169 and the Irish Research Council for Science Engineering and Technology IRCSET International Centre for Graduate Education in Micro and Nano Engineering ICGEE The authors also thank the Xilinx University Programme

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