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Title of Journal: Optoelectron Lett

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Abbravation: Optoelectronics Letters

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Tianjin University of Technology

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DOI

10.1006/jhge.1999.0138

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1993-5013

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Implementation of area optimization precoder in a

Authors: Zhou Liming Zhang Yangan Minglun Zhang Gai Wang Jinnan Zhang Yongqing Huang Ling Li
Publish Date: 2010/11/10
Volume: 6, Issue: 6, Pages: 446-448
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Abstract

In this paper a new model based on an improved Brent Kung BK parallel prefix network PPN algorithm is proposed and realized in the field programmable gate array FPGA This model is employed in the implementation of 20 Gb/s differential quadrature phaseshift keying DQPSK precoder in 40 Gb/s polarization division multiplex PolDM DQPSK system In the computation process the computation complexity area optimization with fanout limited is achieved In the implementation 770 FPGA slice registers are utilized which save about 60 logic resources compared with the previous Kogge Stone KS algorithmThis work has been supported by the National High Technology Research and Development Program of China No2009AA01Z224 the National 111 Project NoB07005 and the Program for Changjiang Scholars and Innovative Research Team in University of China NoIRT0609

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