Authors: Akshat Verma Sandeep Sen
Publish Date: 2008/01/16
Volume: 45, Issue: 2, Pages: 205-235
Abstract
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the IO model of Aggarwal and Vitter Commun ACM 3191116–1127 1988 More than a decade of architectural advancements have led to new features that are not captured in the IO model—most notably the prefetching capability We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional IO models and show how to design optimal algorithms that can attain close to peak memory bandwidth Unlike the inverse of memory latency the memory bandwidth is much closer to the processing speed thereby intelligent use of prefetching can considerably mitigate the IO bottleneck For some fundamental problems our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions Our work also explains more precisely the significantly superior performance of the IO efficient algorithms in systems that support prefetching compared to ones that do not
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