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Title of Journal: J Sign Process Syst Sign Image Video Technol

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1007/bf00161666

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1939-8115

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RealTime Embedded Software Design for Mobile and

Authors: PaoAnn Hsiung ShangWei Lin ChaoSheng Lin
Publish Date: 2008/09/23
Volume: 59, Issue: 1, Pages: 13-32
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Abstract

Currently available application frameworks that target at the automatic design of realtime embedded software are poor in integrating functional and nonfunctional requirements for mobile and ubiquitous systems In this work we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded RealTime Application Framework VERTAF which integrates three techniques namely software componentbased reuse formal synthesis and formal verification The proposed architecture for VERTAF is componentbased which allows plugandplay for the scheduler and the verifier The architecture is also easily extensible because reusable hardware and software design components can be added Application examples developed using VERTAF demonstrate significantly reduced relative design effort which shows how highlevel reuse of software components combined with automatic synthesis and verification increases design productivity

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Other Papers In This Journal:
  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
  6. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  7. Embedded Hypercube Graph Applied to Image Analysis Problems
  8. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  9. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  10. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  11. Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
  12. Editorial
  13. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
  14. Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
  15. Design and Analysis of Hierarchically Modulated BICM-ID Receivers With Low Inter-Layer Interferences
  16. Area Efficient Sequential Decimal Fixed-point Multiplier
  17. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  18. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  19. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  20. An Authentication Technique for Image/Legal Document (ATILD)
  21. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
  22. A High-level Microprocessor Power Modeling Technique Based on Event Signatures
  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
  26. AI Based Network and Radio Resource Management in 5G HetNets
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