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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1002/jso.2930470106

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1939-8115

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DART—a High Level SoftwareDefined Radio Platform

Authors: Martin Palkovic Jeroen Declerck Prabhat Avasare Miguel Glassee Andy Dewilde Praveen Raghavan Antoine Dejonghe Liesbet Van der Perre
Publish Date: 2012/03/25
Volume: 69, Issue: 3, Pages: 317-327
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Abstract

Novel cognitive radio platforms such as IMEC’s COgnitive Baseband RAdio COBRA should ensure the feasibility of multiple streams and their reconfigurability and scalability during runtime The control over these tasks should be dedicated to a runtime controller that reallocates the resources on the platform Eg when the channel conditions change requiring a switching to different modulation and coding scheme or a user starts a new stream Current transaction level models are too detailed for rapid exploration of all runtime options and the highlevel dataflow frameworks such as Kahn process networks lack the dynamism and reconfigurability that is essential for the exploration In this paper we propose the DAtaflow for RunTime DART the highlevel dynamic dataflow platform model framework suited for rapid runtime control development We sketch how to use this framework to develop such a controller in the reactive and more challenging proactive way We derive the component timing based on Instruction Set Simulator ISS simulation and the reconfiguration timing based on Transaction Level Modeling TLM simulation Finally we verify results of our DART approach with full TLM simulation of our platform

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  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
  6. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  7. Embedded Hypercube Graph Applied to Image Analysis Problems
  8. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  9. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  10. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  11. Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
  12. Editorial
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  14. Design and Analysis of Hierarchically Modulated BICM-ID Receivers With Low Inter-Layer Interferences
  15. Area Efficient Sequential Decimal Fixed-point Multiplier
  16. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  17. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  18. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  19. An Authentication Technique for Image/Legal Document (ATILD)
  20. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
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  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
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