Authors: Liu Han Amir Kaivani SeokBum Ko
Publish Date: 2013/07/12
Volume: 75, Issue: 1, Pages: 39-46
Abstract
In this paper a new architecture is proposed to reduce the area cost and power consumption of the decimal fixedpoint multiplier In the proposed sequential architecture the partial product generation and selection cycles are reduced to one Moreover the elaborately selected easy multiples reduce the hardware requirement of the partial products selector Subsequently two partial products are accumulated with the iteration result in a redundant decimal format by a multioperand redundant adder The lowersignificant half digits of the final product are iteratively converted in every cycle On the other hand the highersignificant half digits are converted by a carrypropagation adder in two extra cycles After all the area of the whole architecture is reduced significantly by not only the simpler partial product generation and accumulation architecture but also the less registers The synthesized result shows that the proposed sequential multiplier has a lower area cost and reasonable computation latencyThe authors would like to acknowledge the anonymous reviewers involved in the review of this manuscript This project issupported by the Electrical and Computer Engineering department in University of Saskatchewan and the Natural Science andEngineering Research Council NSERC of Canada
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