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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1016/0260-4779(85)90031-7

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1939-8115

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An Authentication Technique for Image/Legal Docume

Authors: Nabin Ghoshal J K Mandal A Khamrui
Publish Date: 2010/12/07
Volume: 67, Issue: 2, Pages: 187-199
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Abstract

The paper presents an image/legaldocument authentication and secures message transmission technique by embedding message/image/messagedigest into color images Image authentication is done by embedding message/image within the image pixels of source image Legal document authentication is done by embedding the authenticating image and self generated message digest generated from signed document part into the image part of the legal document The position of insertion is chosen within each byte of source image using XOR operation between upper three bits of each source byte and k where k is any number from 0 to 7 Three bits of authenticating message/image/messagedigest are embedded in each byte of source image Fabrication process starts with the dimension of authenticating image followed by message digest MD and ends by embedding the content of authenticating message/image To enhance the security further a layer has also been fabricated by XOR operation of the embedded image with another self generated MD key obtained from the source image The decoding is done by applying the reverse algorithm Experimental results are tested with the aid of Histogram analysis noise analysis standard deviation computation and PSNR IF MSE analysis of the source and embedded image and has been compared with popular existing steganographic algorithms like STools where the proposed ATILD is capable to hide large volume of data than STools and shows better performance The proposed ATILD technique also shows high amount of sustainability against various attacks


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  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
  6. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  7. Embedded Hypercube Graph Applied to Image Analysis Problems
  8. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  9. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  10. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  11. Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
  12. Editorial
  13. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
  14. Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
  15. Design and Analysis of Hierarchically Modulated BICM-ID Receivers With Low Inter-Layer Interferences
  16. Area Efficient Sequential Decimal Fixed-point Multiplier
  17. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  18. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  19. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  20. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
  21. Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
  22. A High-level Microprocessor Power Modeling Technique Based on Event Signatures
  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
  26. AI Based Network and Radio Resource Management in 5G HetNets

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