Matrix Merging Scheme and Efficient Decoding Techn

Authors: MinAn Chao XinYu Shih AnYeu Andy Wu

Publish Date: 2011/06/11

Volume: 68, Issue: 2, Pages: 183-202

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Abstract

Many recent reconfigurable/multimode quasicyclic low density parity check QCLDPC decoder designs have shown appealing implementation results in the literature However most of them are based on datapath multiplexing techniques with ad hoc matrix arrangement There is still room for further interconnection reduction throughput enhancement and a more sophisticated early termination scheme In this paper we will focus on these issues and present a twolevel design approach which optimizes the design at 1 matrix merging level and 2 module design level First direct multiplexing datapaths between multiple modes leads to great overhead on wiring complexity In order to mitigate this problem we merge multiple parity check matrices by proposing an efficient algorithm at matrix merging level which helps to minimize multiplexer and wiring overhead Second for efficient decoding issues we propose two design techniques at module design level One is data wrapping scheme It enhances the decoding throughput by using the datawrapped memory with the proposed reconfigurable dataswitching circuits RDSC to conquer the data alignment problem and achieve multimode reconfigurability The other is the adaptive early termination AET scheme It can save the unnecessary decoding procedures under both highSNR and lowSNR regions Finally to verify our design approach we implement a triplemode LDPC decoder chip which is compatible to IEEE 80211n standard by using UMC 90 nm CMOS technology This chip only occupies 332 mm2 and features high core utilization up to 70 with low power dissipation of 1353 mW The prototyping chip not only validates the proposed approach but also outperforms the stateoftheart QCLDPC decoders for IEEE 80211n systemsThis work was partially supported by the National Science Council of Taiwan under Grant NSC 962220E002011 The authors would like to thank YuHsin Chen and YiJu Chen for simulation codes of the adaptive early termination JenYang Wen for partial RTL coding of the triplemode LDPC decoder design as well as discussions on the data wrapping scheme and ChingDa Chan from National Chip Implementation Center CIC for advices during the backend stage

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