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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1002/chin.201338239

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1939-8115

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Automatic Synthesis of Parsers and Validation of B

Authors: Christophe Lucarz Jonathan Piat Marco Mattavelli
Publish Date: 2009/07/09
Volume: 63, Issue: 2, Pages: 215-225
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Abstract

Video coding technology has evolved in the past years into a variety of different and complex algorithms So far the specifications of such standard algorithms have been done case by case providing monolithic textual and reference software specifications but without paying any attention to the possibility of further improvements of such monolithic standards The MPEG Reconfigurable Video Coding RVC framework is a new ISO/IEC standard currently under its final stage of development aiming at providing video codec specifications at the level of coding tools instead of monolithic descriptions The possibility to select a subset of standard video coding algorithms to specify a decoder that satisfies application specific constraints is very attractive However such possibility to reconfigure codecs requires systematic procedures and tools capable of describing the new bitstream syntaxes of such new codecs Moreover it becomes also necessary to generate the associated parsers capable of parsing the new bitstreams This paper further explains the problem and describes the technologies used to describe new bitstream syntaxes Additionally the paper describes the methodologies and the tools for the validation of bitstream syntaxes descriptions as well as a systematic procedure for automatically synthesizing parsers from the bitstream descriptions

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  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
  6. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  7. Embedded Hypercube Graph Applied to Image Analysis Problems
  8. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  9. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  10. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  11. Editorial
  12. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
  13. Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
  14. Design and Analysis of Hierarchically Modulated BICM-ID Receivers With Low Inter-Layer Interferences
  15. Area Efficient Sequential Decimal Fixed-point Multiplier
  16. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  17. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  18. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  19. An Authentication Technique for Image/Legal Document (ATILD)
  20. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
  21. Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
  22. A High-level Microprocessor Power Modeling Technique Based on Event Signatures
  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
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