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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1002/pol.1960.1204614803

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1939-8115

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An Efficient Architecture for Sequential Monte Car

Authors: Mahdi Shabany
Publish Date: 2011/09/04
Volume: 68, Issue: 3, Pages: 303-315
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Abstract

A pipelined architecture is developed for a Sequential Monte Carlo SMC receiver that performs joint channel estimation and data detection The promising feature of the proposed SMC receiver is achieving the nearbound performance in fading channels without using any decision feedback training or pilot symbols The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks ie the SMC core weight calculator and resampler Hardware efficient/parallel architectures for each functional block including the resampling block is developed The novel feature of the proposed architecture is that makes the execution time of the resampling independent of the distributions of the weights Despite the alternatives in the literature the proposed scheme achieves a very small execution time by pipelining the resampling and sampling steps Moreover it is scalable for high levels of parallelism has lower memory usage fixed routing time and has close to the ideal performance Finally an ASIC implementation of the resampling core is presented in a 013 μm CMOS technology which operates at 200 MHz with 08 mm2 of silicon area


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Other Papers In This Journal:

  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  6. Embedded Hypercube Graph Applied to Image Analysis Problems
  7. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  8. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  9. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  10. Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
  11. Editorial
  12. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
  13. Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
  14. Design and Analysis of Hierarchically Modulated BICM-ID Receivers With Low Inter-Layer Interferences
  15. Area Efficient Sequential Decimal Fixed-point Multiplier
  16. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  17. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  18. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  19. An Authentication Technique for Image/Legal Document (ATILD)
  20. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
  21. Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
  22. A High-level Microprocessor Power Modeling Technique Based on Event Signatures
  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
  26. AI Based Network and Radio Resource Management in 5G HetNets

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