Authors: Mahdi Shabany
Publish Date: 2011/09/04
Volume: 68, Issue: 3, Pages: 303-315
Abstract
A pipelined architecture is developed for a Sequential Monte Carlo SMC receiver that performs joint channel estimation and data detection The promising feature of the proposed SMC receiver is achieving the nearbound performance in fading channels without using any decision feedback training or pilot symbols The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks ie the SMC core weight calculator and resampler Hardware efficient/parallel architectures for each functional block including the resampling block is developed The novel feature of the proposed architecture is that makes the execution time of the resampling independent of the distributions of the weights Despite the alternatives in the literature the proposed scheme achieves a very small execution time by pipelining the resampling and sampling steps Moreover it is scalable for high levels of parallelism has lower memory usage fixed routing time and has close to the ideal performance Finally an ASIC implementation of the resampling core is presented in a 013 μm CMOS technology which operates at 200 MHz with 08 mm2 of silicon area
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