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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1007/bf01919140

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1939-8115

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Utilization of Pipeline Technique in AOP Based Mul

Authors: Morteza Nikooghadam Ali Zakerolhosseini
Publish Date: 2012/09/27
Volume: 72, Issue: 1, Pages: 57-62
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Abstract

Heretofore many AllOnePolynomials AOP based multipliers are proposed over GF2 m Previously proposed multipliers have serial input structure and also suffer from a long critical path delay In this paper we improve AOP based multipliers by reducing the critical path delay and changing the input structure to parallel Initially we modify the wiring of the previously proposed AOP based multipliers This approach reduces the critical path delay from Om to Olog m In order to further reduce this delay from Olog m to O1 the pipeline technique is utilized The efficiency of the proposed architectures is evaluated based on criteria of time latency critical path and space complexity gatelatch number

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