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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1007/s00170-009-2034-7

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1939-8115

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Optimized Implementation of RNS FIR Filters Based

Authors: Salvatore Pontarelli Gian Carlo Cardarilli Marco Re Adelio Salsano
Publish Date: 2010/09/30
Volume: 67, Issue: 3, Pages: 201-212
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Abstract

In this paper optimized Residue Number System RNS arithmetic blocks to better exploit some of the architectural characteristics of the last generation FPGAs are presented The implementation of modulo m adders modulo m constant and general multipliers input and output converters are presented These architectures are based on moduli sets chosen in order to optimally use the 6input LookUp Tables LUTs available in the Complex Logic Blocks CLBs of the new generation FPGAs Experiments based on the implementation of Finite Impulse Response FIR filters characterized by different number of taps and wordlengths shows that the use of RNS together with suitable moduli sets optimally fits the 6input LUTs in the last generation FPGAs architectures

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