Authors: Mojtaba Mahdavi Mahdi Shabany
Publish Date: 2016/06/06
Volume: 88, Issue: 3, Pages: 273-285
Abstract
A novel ultra highthroughput detection algorithm with an efficient VLSI architecture for highorder MIMO detectors in the complex constellations is proposed The main contributions include a new method for the node generation in complexdomain pipelinable sorters and a simple combinational circuit instead of the conventional multipliers which makes the proposed architecture multiplicationfree The proposed design achieves an SNRindependent throughput of 133 Gbps at the clock frequency of 556 MHz in a 013 μm CMOS technology with a near ML performance The implemented design consumes 90 pJ per detected bit with the initial latency of 03 μs Also the synthesis results in a 90 nm CMOS technology prove that the proposed design can achieve the throughput of 20 Gbps Moreover an FPGA platform was developed using a Xilinx ML605 Evaluation board demonstrating a sustained throughput of 33 Gbps at 140 MHz clock frequency As an important feature the proposed architecture can easily be extended to higherorder constellations and can be tailored for lowpower/lowerarea applications at the expense of a lower detection throughput “A less efficient flavor of the algorithm presented in this paper was presented in part in 10 The proposed design in this paper has improved significantly in terms of the proposed algorithm architecture the basic blocks and the final implementation results while presenting comprehensive complexity analysis of the proposed method”
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