Authors: ChunYuan Chu AnYeu Wu
Publish Date: 2011/07/07
Volume: 68, Issue: 2, Pages: 233-245
Abstract
Viterbi decoder is a common module in communication system which has the requirement of low power and low decoding latency The conventional register exchange RE algorithm and memorybased traceback TB algorithm cannot meet both constraints of power and decoding latency In this paper we propose a new Survivor Memory Unit SMU algorithm named State Exchange SE algorithm The SE algorithm uses the traceforward unit TFU to run the decoding operation for low decoding latency Besides we enhance the SE algorithm by the concept of the traceback TB Based on this enhancement we propose two types of SESMU Proposed typeI SESMU has lower register requirement with a long critical path Proposed typeII SESMU can support the high speed requirement with the cost of additional TFUs and latency Both two proposed SESMUs have the decoding latency slightly higher than the decoding latency of RESMU We synthesized the proposed architecture in TSMC 013 um technology Both two approaches have fewer active registers as decoding From the power analysis proposed SESMUs can give a 70 power reduction comparing with RESMU at 100 MHz with the decoding length = 96 The power saving ration will increase further with the longer decoding lengthFinancial supports from the SoC Technology Center STC at Industrial Technology Research Institute ITRI and NSC grant no NSC 96–2219 E002020 are greatly appreciated The material in this paper was presented in part at the VLSIDAT Hsinchu ROC April 2008
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