A Highlevel Microprocessor Power Modeling Techniq

Authors: Peter van Stralen Andy D Pimentel

Publish Date: 2008/11/11

Volume: 60, Issue: 2, Pages: 239-250

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Abstract

This paper presents a technique for highlevel power estimation of microprocessors The technique which is based on abstract execution profiles called ‘event signatures’ operates at a higher level of abstraction than commonlyused instructionset simulator ISS based power estimation methods and should thus be capable of achieving good evaluation performance As a consequence the technique can be very useful in the context of early systemlevel design space exploration In this paper we also compare our power estimation results to those from the instructionlevel simulators Wattch and SimPanalyzer In these experiments we demonstrate that with a good underlying power model the signaturebased power modeling technique can yield accurate estimations a mean error of 31 compared to Wattch in our experiments At the same time our signaturebased power modeling technique is at least an order of magnitude faster than the simulations performed by Wattch or SimPanalyzerThe increasing complexity of modern embedded systems which are more and more based on heterogeneous multiprocessorsystemonchip MPSoC architectures has led to the emergence of systemlevel design A key ingredient of systemlevel design is the notion of highlevel modeling and simulation in which the models allow for capturing the behavior of system components and their interactions at a high level of abstraction As these highlevel models minimize the modeling effort and are optimized for execution speed they can be applied at the early design stages to perform for example architectural design space exploration DSE Such early DSE is of eminent importance as early design choices heavily influence the success or failure of the final productThe Sesame modeling and simulation framework 7 16 facilitates efficient systemlevel DSE of embedded multimedia systems allowing rapid performance evaluation of different architecture designs application to architecture mappings and hardware/software partitionings Key to this flexibility is the separation of application and architecture models together with an explicit mapping step to map an application model onto an architecture modelUntil now the Sesame modeling and simulation framework has purely focused on the performance analysis of multimedia MPSoC architectures Evidently to make good design tradeoffs also power consumption needs to be taken into account during the process of DSE Therefore this paper presents the first step towards including systemlevel power models in Sesame More specifically we elaborate on the concept of event signatures which was recently introduced in 24 that allows for highlevel power modeling of microprocessors and their local memory hierarchy This signaturebased power modeling operates at a higher level of abstraction than commonlyused instructionset simulator ISS based power models and should thus be capable of achieving good evaluation performance This is important since ISSbased power estimation generally is not suited for early DSE as it is too slow for evaluating a large design space the evaluation of a single design point via ISSbased simulation with a realistic benchmark program may take in the order of seconds to hundreds of seconds 12 Moreover unlike many other highlevel power estimation techniques our signaturebased power modeling technique still incorporates an explicit microarchitecture model of the processor and thus is able to perform microarchitectural DSE as wellUsing several experiments we compare the results from our signaturebased power modeling with those from Wattch 6 and SimPanalyzer 1 which are widelyused ISSbased power analysis tools Here we show that with a good underlying power model the signaturebased power modeling technique can yield accurate estimations while being at least an order of magnitude faster than Wattch or SimPanalyzer In order to perform systemlevel power modeling of an entire MPSoC the next step not addressed in this paper will be to extend the power modeling framework with models for the interconnect and possible dedicated components in the MPSoCIn the next section we briefly describe the Sesame framework Section 3 introduces the concept of event signatures and explains how they can be used for highlevel power modeling of microprocessors In Section 4 we describe the power models used for modeling different aspects of microprocessors Section 5 presents a number of experiments in which we compare the results from our models against those from Wattch and SimPanalyzer In Section 6 we describe related work after which Section 7 concludes the paperFor application modeling Sesame uses the Kahn Process Network KPN model of computation 10 which fits well to the multimedia application domain In a KPN parallel processes communicate with each other via unbounded FIFO channels where reading from these channels is blocking and writing is nonblocking The computational behavior of an application is captured by instrumenting the code of each Kahn process with annotations that describe the application’s computational actions The reading from and writing to Kahn channels represent the communication behavior of a process within the application model By executing the KPN model each Kahn process records its actions in order to generate its own trace of application events These application events are an abstract representation of the workload that is imposed on the architecture and drive the underlying architecture model Application events typically are coarse grained such as ExecuteDCT which represents the execution of a Discrete Cosine Transform DCT or Readchannel idpixelblock which represents the reading of a pixel block from communication channel channel id

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