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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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DOI

10.1002/pds.3514

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1939-8115

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Design and Analysis of Hierarchically Modulated BI

Authors: M Tschauner Md F T Oshim M Adrat M Antweiler B Eschbach P Vary
Publish Date: 2017/01/31
Volume: 89, Issue: 1, Pages: 145-161
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Abstract

In this article we present a novel methodology to optimize Hierarchically Modulated BitInterleaved Coded Modulation with Iterative Decoding HMBICMID This methodology allows designing a receiver which supports several configurations Each configuration is able to decode the same transmitted signal over the air with different fidelity This concept permits using radios with varying processing capabilities eg handheld radios vehicular based radios etc However earlier simulation results have shown that HMBICMID loses if compared to nonhierarchical schemes in Bit Error Rate BER performance due to InterLayer Interferences and design restrictions Our proposed iterative tunable procedure optimizes hierarchical modulation schemes considering two criteria the Harmonic Mean of the minimum squared Euclidean Distance and the bit error probability The optimization is done by moving critical constellation points towards the optimal direction A novel modulation scheme has been found and simulation results show an improved asymptotic BER performance in a wide range of channel conditions for an exemplary twolayered HMBICMID Finally we present an analysis of HMBICMID in context of Extrinsic Information Transfer Charts


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  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
  6. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  7. Embedded Hypercube Graph Applied to Image Analysis Problems
  8. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  9. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  10. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  11. Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
  12. Editorial
  13. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
  14. Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
  15. Area Efficient Sequential Decimal Fixed-point Multiplier
  16. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  17. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  18. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  19. An Authentication Technique for Image/Legal Document (ATILD)
  20. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
  21. Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
  22. A High-level Microprocessor Power Modeling Technique Based on Event Signatures
  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
  26. AI Based Network and Radio Resource Management in 5G HetNets

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