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Title of Journal: J Sign Process Syst

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Abbravation: Journal of Signal Processing Systems

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Springer US

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1939-8115

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Editorial

Authors: Mladen Berekovic Andy D Pimentel
Publish Date: 2009/01/17
Volume: 60, Issue: 2, Pages: 147-148
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Abstract

This special issue contains a selection of the best papers from the 2007 IEEE ESTIMedia workshop which is part of the Embedded Systems Week ESTIMedia is intended to be a forum for specialists from academia and industry for defining design methodologies architectures and circuits for future embedded multimedia systems Today the design process for highend multimedia systems has become a crucial bottleneck due to the increasing complexity of both the software and the underlying hardware coupled with shortened timetomarket pressures While there has been a notable growth in the use and applications of multimedia systems and in the evolution of systemonchip design technology there are still enormous opportunities for improving design productivity in this domain Given this backdrop the aim of ESTIMedia is to bring together people from different multimediarelated research communities eg software architectures realtime systems DSP compilers multimedia applications who have worked separately but did not interact sufficiently to address the challenges facing the design of hardware and software for multimedia systemsIn the 2007 edition of ESTIMedia the workshop featured 19 highquality technical papers which have been selected after a thorough review process in which each submitted paper received on average 42 reviews From these 19 papers we selected seven papers for this special issue which were again subjected to a rigorous review process The selected papers cover a wide range of topics in the scope of embedded multimedia systemsIn “EnergyEfficient Streaming Using NonVolatile Memory” Mohammed G Khatib et al show that energy can be saved for predominantly streaming workloads by connecting the system’s disk to the DRAM via a large nonvolatile memory NVM In their approach the NVM acts as a traffic reshaper from the disk to the DRAMIn “Runtime Task Overlapping on Multiprocessor Platforms” Zhe Ma et al address dynamic Paretooptimal scheduling on multiprocessor systems They propose a simple yet powerful online technique that performs task overlapping by runtime subtask rescheduling By doing so a multiprocessor system with concurrent tasks can achieve better performance without extra energy consumptionIn “Optimizing the H264/AVC Video Encoder Application Structure for Reconfigurable and ApplicationSpecific Platforms” Muhammad Shafique et al propose an optimized application structure for the H264 encoder which is suitable for applicationspecific and reconfigurable hardware platforms The proposed application structural optimization for the computational reduction of the Motion Compensated Interpolation is independent of the actual hardware platform that is used for executionIn “Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories” Yuriko Ishitobi et al propose a code placement problem its Integer Linear Programming formulation and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core onchip and offchip memories The approach exploits a noncacheable memory region for an effective use of cache memory and as a result reduces the number of offchip accessesIn “Still Image Processing on CoarseGrained Reconfigurable Array Architectures” Matthias Hartmann et al investigate the mapping of two typical image processing algorithms wavelet encoding and decoding and TIFF compression on a novel type of coarsegrained reconfigurable array architectures ADRES and its corresponding DRESC compiler in a systematic wayIn “A Highlevel Microprocessor Power Modeling Technique based on Event Signatures” Peter van Stralen et al present a technique for highlevel power estimation of microprocessors The technique operates at a higher level of abstraction than commonlyused instructionset simulator based power estimation methods thus achieving good evaluation performance As a consequence the technique can be useful in the context of early systemlevel design space exploration of multimedia systemsIn “A Safari Through the MPSoC RunTime Management Jungle” Vincent Nollet et al provide a detailed survey on MPSoC runtime management functionality and its design space tradeoffs They substantiate the runtime components and the implementation tradeoffs with academic stateoftheart solutions and give a brief overview of some industrial multiprocessor runtime management examplesWe would like to thank all the authors who submitted manuscripts for this special issue Special thanks go to all the reviewers for their valuable comments criticism and suggestions The investment of their time and insight is very much appreciated and helped to generate this selection of high quality technical papers


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Other Papers In This Journal:

  1. Biometric-oriented Iris Identification Based on Mathematical Morphology
  2. Tracking Forecast Memories for Stochastic Decoding
  3. Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
  4. Power Efficient Signal Processing for mmWave 5G Systems
  5. An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
  6. Energy Efficiency Optimization for Communication of Air-Based Information Network with Guaranteed Timing Constraints
  7. Embedded Hypercube Graph Applied to Image Analysis Problems
  8. The Rate-Distortion Optimized Compressive Sensing for Image Coding
  9. Times Square – Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
  10. A 13 Gbps, 0.13 μ m CMOS, Multiplication-Free MIMO Detector
  11. Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
  12. DART—a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
  13. Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
  14. Design and Analysis of Hierarchically Modulated BICM-ID Receivers With Low Inter-Layer Interferences
  15. Area Efficient Sequential Decimal Fixed-point Multiplier
  16. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
  17. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder
  18. Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
  19. An Authentication Technique for Image/Legal Document (ATILD)
  20. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
  21. Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
  22. A High-level Microprocessor Power Modeling Technique Based on Event Signatures
  23. Optimized Implementation of RNS FIR Filters Based on FPGAs
  24. Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
  25. Dynamic Spectrum Access is the Solution: What’s the Problem?
  26. AI Based Network and Radio Resource Management in 5G HetNets

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