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Title of Journal: J Comput Electron

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Abbravation: Journal of Computational Electronics

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Springer US

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DOI

10.1007/978-1-4615-2095-5_14

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1572-8137

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Dielectric pocket double gate junctionless FET a

Authors: Balraj Singh Deepti Gola Ekta Goel Sanjay Kumar Kunal Singh Satyabrata Jit
Publish Date: 2016/02/29
Volume: 15, Issue: 2, Pages: 502-507
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Abstract

In this paper we report the TCAD based simulation of a new doublegate junctionless FETs DGJLFETs structure incorporating dielectric pockets DPs at the source and drain ends The proposed structure not only improves the ON to OFF drain current ratio by sim 900  subthreshold swing characteristics by sim 12  and Drain Induced Barrier Lowering DIBL by sim 56  over the conventional DGJLFETs ie without DPs but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs Since only little work has been carried out on the performance optimization of the JLFETs the present work is believed to be very useful for designing the lowpower VLSI circuits using DPDG JLFETs with improved performance

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