Paper Search Console

Home Search Page About Contact

Journal Title

Title of Journal: Analog Integr Circ Sig Process

Search In Journal Title:

Abbravation: Analog Integrated Circuits and Signal Processing

Search In Journal Abbravation:

Publisher

Kluwer Academic Publishers

Search In Publisher:

DOI

10.1007/s00383-005-1544-0

Search In DOI:

ISSN

1573-1979

Search In ISSN:
Search In Title Of Papers:

A lowcost programmable clock generator for switch

Authors: W F Lee P K Chan
Publish Date: 2006/04/03
Volume: 47, Issue: 3, Pages: 247-257
PDF Link

Abstract

This paper presents two improved circuit techniques that allow the design of a lowcost programmable clock generator using a ring oscillator for lowfrequency switchedcapacitor applications The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller currentstarved inverter ring oscillator For identical values of integrated components in implementation the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional currentstarved inverter ring oscillator This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixedsignal circuits The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit The experimental results have verified that the programming range of 56 kHz to 1042 MHz is achieved using discretestep tuning on small capacitor values from 0375 pF to 5625 pF together with frequency division by four divider stages whilst the jitter is less than 300 ps at ±10 variation in a 5 V supply in the entire tuning rangeWing Foon Lee was born in Singapore He had worked as an application engineer for more than two years He received his BEng MEng and PhD degrees in Electrical Electronic Engineering from Nanyang Technological University Singapore in 1996 1999 and 2005 respectively His research interest is on low power analog circuit design high precision readout circuits and signalconditioning circuits for sensor applicationsP K Chan was born in Hong Kong He received the BSc Hons degree from the University of Essex Colchester UK in 1987 the MSc degree from the University of Manchester Institute of Science and Technology UMIST Manchester UK in 1988 and the PhD degree from the University of Plymouth UK in 1992 From 1989 to 1992 he was a Research Assistant with the University of Plymouth working in the area of MOS continuoustime filters In 1993 he joined the Institute of Microelectronics IME as a Member Technical Staff where he designed CMOS sensor interfaces for industrial applications In 1996 He was a Staff Engineer with Motorola Singapore where he developed the magnetic write channel for Motorola 1st generation harddisk preamplifier He joined Nanyang Technological University NTU Singapore in 1997 where he is currently an Associate Professor in the School of Electrical and Electronic Engineering and Program Director analog/mixedsignal IC and applications for the Center for Integrated Circuits and Systems CICS He holds four patents and is an IC Design Consultant to local and multinational companies in Singapore He has also conducted numerous IC design short courses to the industrial companies and design centers His research interests include circuit theory amplifier frequency compensation techniques sensing interfaces for integrated sensors biomedical circuits and systems integrated filters and data converters

Keywords:

References

.
Search In Abstract Of Papers:
Other Papers In This Journal:
  1. Wide-locking range ÷3 series-tuned injection-locked frequency divider
  2. Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture
  3. Analytical modeling methodology for ultrawideband low noise amplifiers with generalized filter-based impedance matching
  4. Low-voltage low-power improved linearity CMOS active resistor circuits
  5. Systematic design of analog integrated circuits using ant colony algorithm based on noise optimization
  6. Clock jitter impact on the performance of general charge sampling amplifiers
  7. Design of PR NMDFB based up and down converters for transmit downlink and receive uplink of combined 3GPP LTE and UMTS radios
  8. Automatic tuning of digitally-controllable positive-feedback OTAs in continuous-time sigma–delta modulators
  9. The “Analog Journal” celebrates its 20th Anniversary!
  10. Power fingerprinting in SDR integrity assessment for security and regulatory compliance
  11. Voltage mode third order quadrature oscillators using OTRAs
  12. Construction of CDBA and CDTA behavioral models and the applications in symbolic circuits analysis
  13. High speed BiCMOS linear driver core for segmented InP Mach-Zehnder modulators
  14. Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA
  15. A 2.4-GHz low power polar transmitter for wireless body area network applications
  16. A 1-mW K-band gate AC-coupled VCO with 0.25 V supply voltage
  17. A technique for improving gain and noise figure of common-gate wideband LNAs
  18. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  19. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  20. Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC
  21. Implementation of an SDR system using an MPI-based GPU cluster for WiMAX and LTE
  22. A digital processor for full calibration of pipelined ADCs
  23. A wide-range VCO with an automatic frequency, amplitude and gain calibration loop
  24. A digitally-assisted error compensation grouping method for element matching improvement in data converters
  25. Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror
  26. A novel design of local-feedback MOS transconductor using techniques for cancellation of mobility degradation and linearization of differential output current characteristic
  27. A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers
  28. A high speed four-stage operational amplifier in 65 nm CMOS
  29. Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages
  30. Quantum-inspired evolutionary algorithm for analog test point selection
  31. A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
  32. An adaptive voltage scaling DC–DC converter based on embedded pulse skip modulation
  33. High-Gain Class-AB OTA with Low Quiescent Current
  34. A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver
  35. A self-powered power conditioning circuit for battery-free energy scavenging applications
  36. Fully integrated 1.2-μA and 13-μA quiescent current LDOs with improved transient response
  37. On the design of active inductors with current-controlled voltage sources
  38. Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic
  39. New RF power amplifiers modeling and identification for wideband applications
  40. Novel detector implementations for 3G LTE downlink and uplink
  41. A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
  42. Comment on “realization of series and parallel R-L and C-D impedances using single differential voltage current conveyor”
  43. A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system
  44. A broad-band V-band power amplifier using a reduced access-resistance transistor layout in 65-nm CMOS
  45. Comparison of high impedance input topologies with low EMI susceptibility
  46. Nonlinear modeling and analysis of a Doherty power amplifier driven by non-constant envelope signals
  47. Hybrid delta-sigma ADC
  48. A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS
  49. Introduction to the Special issue on IEEE-Latin American Symposium on Circuits and Systems
Search Result: