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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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DOI

10.1016/j.ajo.2011.10.020

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ISSN

1573-1979

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Evaluating the use of adder compressors for power

Authors: Cláudio Machado Diniz Mateus Beck Fonseca Eduardo Antonio César da Costa Sergio Bampi
Publish Date: 2016/05/20
Volume: 89, Issue: 1, Pages: 111-120
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Abstract

The recent High Efficient Video Coding HEVC standard introduces a new and complex interpolation filter for fractionalpixel motion estimation and motion compensation Recent works propose hardware architectures to accelerate the interpolation filter employing interpolation datapaths with many adders in parallel Adder compressors are powerefficient operators that are applied when intermediate additions are not required which is the case for interpolation filters This work evaluates the use of different 72 and 82 adder compressors structures in the interpolation datapaths of a recent HEVC interpolation filter architecture targeting power efficiency Results show that 72 adder compressor composed with basic 42 and 32 adder compressors and 82 adder compressor composed with basic 42 adder compressors reduce power delay product by 16 and 19  respectively compared with adders generated by the synthesis tool These adder compressors achieved the best results in terms of PDP compared with many classical adders The full interpolation filter architecture using the best adder compressors dissipates 99671 µW of power and consumes 2821 pJ of energy per operation

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