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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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DOI

10.1007/s00432-012-1246-7

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1573-1979

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A highfrequency CMOS multimodulus divider for PL

Authors: ChingYuan Yang
Publish Date: 2008/03/15
Volume: 55, Issue: 2, Pages: 155-162
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Abstract

A highfrequency divideby256–271 programmable divider is presented with the improved timing of the multimodulus divider structure and the highspeed embedded flipflops The D flipflop and logic flipflop are proposed by using a fast pipeline technique which contains singlephase edgetriggered ratioed and highspeed technologies The circuits achieve highspeed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements By the way it is suitable for realizing highspeed synchronous counters The programmable divider using proposed flipflops is measured in 025μm CMOS technology with the operating clock frequency reaching as high as 47 GHz under the supply voltage of 3VThe author would like to thank the SHARP Technology Company Japan for the fabrication of the chip and Prof SI Liu Department of Electronic Engineering National Taiwan University Taiwan for discussion about this paper This work was supported by the National Science Council Taiwan under Research Grant NSC952220E005003

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