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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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1573-1979

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A 1GS/s 6bit folding and interpolating ADC in 0

Authors: Li Lin Junyan Ren Kai Zhu Fan Ye
Publish Date: 2008/10/29
Volume: 58, Issue: 1, Pages: 71-76
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Abstract

A 1GS/s 6bit twochannel timeinterleaved folding and interpolating analogtodigital converter ADC is presented in this article For low voltage applications inputconnectionimproved active interpolating amplifiers and cascaded folding amplifiers have been applied A single frontend trackandhold T/H circuit is used to avoid the samplingtime mismatches between the channels When supplied with 14 V the circuit achieves signaltonoiseplusdistortion ratio SNDR of 3074 dB and spurious free dynamic range SFDR of 3691 dB and consumes a power of 66 mW with 500MHz input and 1GS/s sampling rate Differential nonlinearity DNL and integral nonlinearity INL are 057 and 081 LSB respectively The figure of merit FoM is 175 pJ/conversionstep The ADC circuit is prototyped in 013μm CMOS process and occupies a core area of 045 mm2This work is supported by National Natural Science Foundations of China No 90407003 Science and Technology Commission of Shanghai Municipality No 067062003 No 08XD14007 and ShanghaiApplied Materials Research and Development Fund No 06SA15 No 07SA16

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