Authors: Harish Valapala Paul M Furth
Publish Date: 2013/09/29
Volume: 78, Issue: 2, Pages: 287-297
Abstract
We introduce two extremely low quiescent current I Q lowdropout LDO voltage regulators The Low I Q LDO LI Q LDO uses 13 μA of total quiescent current and is designed for a maximum load current of 50 mA The Micro I Q LDO MI Q LDO uses only 12 μA of total quiescent current and is designed for a maximum load current of 5 mA Detailed pole/zero analysis is performed to aid in the design of the LDOs Two LHP zeros cancel the two nondominant poles which extend the bandwidth and improve transient response Both designs are fully integrated stabilized with an onchip capacitive load of 100 pF In load transient the total variation in output voltage for LI Q LDO and MI Q LDO is 1 V and 950 mV respectively and the total line transient variation is 668 and 599 mV respectively Both designs occupy an area of 026 mm2 in a 05μm CMOS process Two processindependent figures of merit are proposed to compare LI Q LDO and MI Q LDO with other published work
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