Paper Search Console

Home Search Page About Contact

Journal Title

Title of Journal: Analog Integr Circ Sig Process

Search In Journal Title:

Abbravation: Analog Integrated Circuits and Signal Processing

Search In Journal Abbravation:

Publisher

Springer US

Search In Publisher:

DOI

10.1007/jhep05(2015)016

Search In DOI:

ISSN

1573-1979

Search In ISSN:
Search In Title Of Papers:

Systematic design of analog integrated circuits us

Authors: Meysam Akbari Mohammad Shokouhifar Omid Hashemipour Ali Jalali Alireza Hassanzadeh
Publish Date: 2015/12/29
Volume: 86, Issue: 2, Pages: 327-339
PDF Link

Abstract

In this paper a systematic design approach based on noise optimization with power consumption minimization for operational transconductance amplifiers OTAs is presented In this methodology HSPICE and ant colony optimization ACO algorithm are used as simulation tool and optimization method respectively By rewriting the thermal noise flicker noise corner frequency and other specifications of the OTA based on the Gm/Id characteristic in all regions of transistor operation noise optimization beside the power minimization is achieved in a reasonable simulation time In this approach ACO is applied in order to optimize the design variables aim at minimizing the input referred noise and power consumption The design methodology is successfully used for systematic design and optimization of a CMOS Miller folded cascade amplifier using 018 µm CMOS technology in the three regions of amplifier operation Simulation results confirm the accuracy of the theoretical analysis in the presented design methodologyWe declare that this manuscript is original has not been published before and is not currently being considered for publication elsewhere We confirm that the manuscript has been read and approved by all named authors and that there are no other persons who satisfied the criteria for authorship but are not listed We further confirm that the order of authors listed in the manuscript has been approved by all of us We understand that the corresponding author is the sole contact for the Editorial process He/she is responsible for communicating with the other authors about progress submissions of revisions and final approval of proofs


Keywords:

References


.
Search In Abstract Of Papers:
Other Papers In This Journal:

  1. Wide-locking range ÷3 series-tuned injection-locked frequency divider
  2. Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture
  3. Analytical modeling methodology for ultrawideband low noise amplifiers with generalized filter-based impedance matching
  4. Low-voltage low-power improved linearity CMOS active resistor circuits
  5. Clock jitter impact on the performance of general charge sampling amplifiers
  6. Design of PR NMDFB based up and down converters for transmit downlink and receive uplink of combined 3GPP LTE and UMTS radios
  7. Automatic tuning of digitally-controllable positive-feedback OTAs in continuous-time sigma–delta modulators
  8. The “Analog Journal” celebrates its 20th Anniversary!
  9. Power fingerprinting in SDR integrity assessment for security and regulatory compliance
  10. Voltage mode third order quadrature oscillators using OTRAs
  11. Construction of CDBA and CDTA behavioral models and the applications in symbolic circuits analysis
  12. High speed BiCMOS linear driver core for segmented InP Mach-Zehnder modulators
  13. Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA
  14. A 2.4-GHz low power polar transmitter for wireless body area network applications
  15. A 1-mW K-band gate AC-coupled VCO with 0.25 V supply voltage
  16. A technique for improving gain and noise figure of common-gate wideband LNAs
  17. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  18. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  19. Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC
  20. Implementation of an SDR system using an MPI-based GPU cluster for WiMAX and LTE
  21. A digital processor for full calibration of pipelined ADCs
  22. A wide-range VCO with an automatic frequency, amplitude and gain calibration loop
  23. A digitally-assisted error compensation grouping method for element matching improvement in data converters
  24. Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror
  25. A novel design of local-feedback MOS transconductor using techniques for cancellation of mobility degradation and linearization of differential output current characteristic
  26. A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers
  27. A high speed four-stage operational amplifier in 65 nm CMOS
  28. Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages
  29. A low-cost programmable clock generator for switched-capacitor circuit applications
  30. Quantum-inspired evolutionary algorithm for analog test point selection
  31. A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
  32. An adaptive voltage scaling DC–DC converter based on embedded pulse skip modulation
  33. High-Gain Class-AB OTA with Low Quiescent Current
  34. A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver
  35. A self-powered power conditioning circuit for battery-free energy scavenging applications
  36. Fully integrated 1.2-μA and 13-μA quiescent current LDOs with improved transient response
  37. On the design of active inductors with current-controlled voltage sources
  38. Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic
  39. New RF power amplifiers modeling and identification for wideband applications
  40. Novel detector implementations for 3G LTE downlink and uplink
  41. A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
  42. Comment on “realization of series and parallel R-L and C-D impedances using single differential voltage current conveyor”
  43. A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system
  44. A broad-band V-band power amplifier using a reduced access-resistance transistor layout in 65-nm CMOS
  45. Comparison of high impedance input topologies with low EMI susceptibility
  46. Nonlinear modeling and analysis of a Doherty power amplifier driven by non-constant envelope signals
  47. Hybrid delta-sigma ADC
  48. A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS
  49. Introduction to the Special issue on IEEE-Latin American Symposium on Circuits and Systems

Search Result: