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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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DOI

10.1002/pssb.200982001

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1573-1979

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A 24GHz low power polar transmitter for wireless

Authors: Vladimir Kopta Erwan Le Roux Franz Pengg Christian Enz
Publish Date: 2014/10/14
Volume: 81, Issue: 3, Pages: 657-666
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Abstract

A 24 GHz low power polar transmitter is proposed in this paper A dynamic biasing circuit controlled by a digital envelope signal is used as a direct digitaltoRF envelope converter It effectively linearizes the inputoutput characteristic of the overdriven cascode classC power amplifier used as the output stage by dynamically adjusting the bias voltage of the cascode transistor An equivalent baseband model of the transmitter is presented and used to optimize system parameters and give initial assessment of the achievable performance in terms of efficiency and linearity Based on these simulations parameters for transistorlevel implementation of the bias circuit are derived The transmitter is designed in a 65 nm CMOS technology The post layout simulations indicate that the transmitter successfully meets the requirements of the IEEE 802156 standard for wireless body area networks The simulated amplifier consumes 475 mA from a 12 V supply while delivering 145 dBm of output power with a peak efficiency of 24  The entire transmitter including the PLL consumes 75 mA

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