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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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DOI

10.1007/978-3-642-77648-9_13

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1573-1979

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A digital processor for full calibration of pipeli

Authors: Mohammad Fardad Javad Frounchi Ghader Karimian
Publish Date: 2011/07/23
Volume: 70, Issue: 3, Pages: 347-356
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Abstract

In this paper a digital processor is presented for full calibration of pipeline ADCs The main idea is to find an inverse model of ADC errors by using small number of the measured codes This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital postprocessing of the output bits Some function approximation algorithms are tested and their performances are evaluated To verify the algorithms a 12bit pipelined ADC based on 15bit per stage architecture is simulated with 12 nonideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency The selected algorithm has been implemented on a Virtex4 LX25 FPGA from Xilinx The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 455 to 90 dB The calibration processor also improves the integral nonlinearity of the ADC

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