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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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DOI

10.1016/0008-8749(81)90372-5

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1573-1979

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Design of a laminated current cell relocation 12b

Authors: Junho Moon Minkyu Song Seungchul Shin Kyungho Moon Byungha Park
Publish Date: 2009/09/16
Volume: 63, Issue: 3, Pages: 407-414
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Abstract

A compact and low power 12bit 300 MS/s current steering CMOS D/A converter is presented The architecture of the D/A converter is based on the current steering 6 + 6 segmented type with a laminated current cell relocation technique In order to improve the linearity and glitch noise a high output impedance analog current cell is designed Furthermore for the purpose of reducing the chip area and power dissipation a noble merged switching logic and a compact layout technique are proposed To verify its performance the chip was fabricated with 013 μm thickgate 1poly 6metal Nwell Samsung CMOS technology The effective chip area is 026 mm2 510 × 510 μm with a power consumption of 100 mW The measured INL and DNL are within ±3LSB and ±1LSB respectively The measured SFDR is about 70 dB when the input frequency is 1 MHz at a clock frequency of 300 MHzThe authors are thankful for the support from Samsung Electronics Co Ltd and this research was supported by the MKE Ministry of Knowledge Economy Korea under the ITRC Information Technology Research Center support program supervised by IITA Institute for Information Technology Advancement IITA2009C109009020012

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