Paper Search Console

Home Search Page About Contact

Journal Title

Title of Journal: Analog Integr Circ Sig Process

Search In Journal Title:

Abbravation: Analog Integrated Circuits and Signal Processing

Search In Journal Abbravation:

Publisher

Springer US

Search In Publisher:

DOI

10.1006/jpdc.1993.1073

Search In DOI:

ISSN

1573-1979

Search In ISSN:
Search In Title Of Papers:

New RF power amplifiers modeling and identificatio

Authors: Smail Bachir Nicusor E Calinoiu Claude Duvanaud
Publish Date: 2015/04/02
Volume: 83, Issue: 2, Pages: 161-172
PDF Link

Abstract

This paper presents a new timedomain model of radio frequency power amplifiers RFPA for wideband applications The proposed model identification requires a set of characterization procedures of a memory polynomial model with delay taps for a twotone test This first characterized model is described using amplitude AM/AM and phase AM/PM characteristics including delay and gain parameters which is able to reproduce distortion sideband asymmetries A twotone signal with varying tone spacings is used to find the frequency response of parameters on each nonlinearity order These response are used to estimate equivalent digital filters giving the final structure of a wideband model The measurement tests on a Class AB −185 GHz RFPA from advanced semiconductor business with various multitone signals show that the proposed architecture describes PA nonlinearities and memory effects with a high level of accuracy

Keywords:

References

.
Search In Abstract Of Papers:
Other Papers In This Journal:
  1. Wide-locking range ÷3 series-tuned injection-locked frequency divider
  2. Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture
  3. Analytical modeling methodology for ultrawideband low noise amplifiers with generalized filter-based impedance matching
  4. Low-voltage low-power improved linearity CMOS active resistor circuits
  5. Systematic design of analog integrated circuits using ant colony algorithm based on noise optimization
  6. Clock jitter impact on the performance of general charge sampling amplifiers
  7. Design of PR NMDFB based up and down converters for transmit downlink and receive uplink of combined 3GPP LTE and UMTS radios
  8. Automatic tuning of digitally-controllable positive-feedback OTAs in continuous-time sigma–delta modulators
  9. The “Analog Journal” celebrates its 20th Anniversary!
  10. Power fingerprinting in SDR integrity assessment for security and regulatory compliance
  11. Voltage mode third order quadrature oscillators using OTRAs
  12. Construction of CDBA and CDTA behavioral models and the applications in symbolic circuits analysis
  13. High speed BiCMOS linear driver core for segmented InP Mach-Zehnder modulators
  14. Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA
  15. A 2.4-GHz low power polar transmitter for wireless body area network applications
  16. A 1-mW K-band gate AC-coupled VCO with 0.25 V supply voltage
  17. A technique for improving gain and noise figure of common-gate wideband LNAs
  18. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  19. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  20. Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC
  21. Implementation of an SDR system using an MPI-based GPU cluster for WiMAX and LTE
  22. A digital processor for full calibration of pipelined ADCs
  23. A wide-range VCO with an automatic frequency, amplitude and gain calibration loop
  24. A digitally-assisted error compensation grouping method for element matching improvement in data converters
  25. Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror
  26. A novel design of local-feedback MOS transconductor using techniques for cancellation of mobility degradation and linearization of differential output current characteristic
  27. A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers
  28. A high speed four-stage operational amplifier in 65 nm CMOS
  29. Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages
  30. A low-cost programmable clock generator for switched-capacitor circuit applications
  31. Quantum-inspired evolutionary algorithm for analog test point selection
  32. A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
  33. An adaptive voltage scaling DC–DC converter based on embedded pulse skip modulation
  34. High-Gain Class-AB OTA with Low Quiescent Current
  35. A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver
  36. A self-powered power conditioning circuit for battery-free energy scavenging applications
  37. Fully integrated 1.2-μA and 13-μA quiescent current LDOs with improved transient response
  38. On the design of active inductors with current-controlled voltage sources
  39. Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic
  40. Novel detector implementations for 3G LTE downlink and uplink
  41. A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
  42. Comment on “realization of series and parallel R-L and C-D impedances using single differential voltage current conveyor”
  43. A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system
  44. A broad-band V-band power amplifier using a reduced access-resistance transistor layout in 65-nm CMOS
  45. Comparison of high impedance input topologies with low EMI susceptibility
  46. Nonlinear modeling and analysis of a Doherty power amplifier driven by non-constant envelope signals
  47. Hybrid delta-sigma ADC
  48. A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS
  49. Introduction to the Special issue on IEEE-Latin American Symposium on Circuits and Systems
Search Result: