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Title of Journal: Analog Integr Circ Sig Process

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Abbravation: Analog Integrated Circuits and Signal Processing

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Springer US

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DOI

10.1016/j.aim.2010.12.017

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1573-1979

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A lowpower transmissiongatebased 16bit multipl

Authors: Flavio Carbognani Felix Buergin Norbert Felber Hubert Kaeslin Wolfgang Fichtner
Publish Date: 2007/10/09
Volume: 56, Issue: 1-2, Pages: 5-12
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Abstract

The most widespread 16bit multiplier architectures are compared in terms of area occupation dissipated energy and EDP EnergyDelay Product in view of lowpower lowvoltage signal processing for digital hearing aids and similar applications Transistorlevel simulations including backannotated wire parasitics confirm that the propagation of glitches along uneven and reconvergent paths results in large unproductive node activity Because of their shorter fulladder chains Wallacetree multipliers indeed dissipate less energy than the carrysave CSM and other traditional array multipliers 60 µW/MHz versus 109 µW/MHz and more for 025 µm CMOS technology at 075 V By combining the Wallacetree architecture with transmission gates TGs a new approach is proposed to improve the energy efficiency further 31 µW/MHz beyond recently published lowpower architectures Besides the reduction of the overall capacitance minimumsized transmission gate fulladders act as RClowpass filters that attenuate undesired switching Finally minimum size TGs increase the V dd to ground resistance hence decreasing leakage dissipation 055 nW versus 084 nW in CSM and 094 nW in Wallace

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