Paper Search Console

Home Search Page About Contact

Journal Title

Title of Journal: Analog Integr Circ Sig Process

Search In Journal Title:

Abbravation: Analog Integrated Circuits and Signal Processing

Search In Journal Abbravation:

Publisher

Springer US

Search In Publisher:

DOI

10.1007/s11137-005-0037-2

Search In DOI:

ISSN

1573-1979

Search In ISSN:
Search In Title Of Papers:

Power fingerprinting in SDR integrity assessment f

Authors: Carlos R Aguayo González Jeffrey H Reed
Publish Date: 2011/09/29
Volume: 69, Issue: 2-3, Pages: 307-
PDF Link

Abstract

SoftwareDefined Radio SDR provides a flexible platform that facilitates radio resource management and enables new technologies and applications Unfortunately their reliance on software implementations makes them vulnerable to malicious software attacks that could impact their spectral emissions and disclose sensitive information It is of critical importance for the widespread deployment of SDR to develop technologies that enable effective integrity assessment of communications platforms and timely detection of malicious intrusions We provide further evidence of the feasibility of a novel approach called Power Fingerprinting PFP that enables an effective mechanism to perform integrity assessment of SDR PFP relies on an external monitor that captures finegrained measurements of the processor’s power consumption and compares them against stored signatures from trusted software by applying pattern recognition and signal detection techniques Because it is implemented by an external monitor PFP causes minimal disruption on the target system and also provides the necessary isolation to protect against malicious attacks to the monitor itself Finegranularity measurements deliver improved visibility into the execution status and make the PFP monitor difficult to evade while the reliance on anomaly detection from trusted references makes it effective against zeroday attacks We present the results of different feasibility experiments that support the applicability of PFP to SDR integrity assessment In the first experiment a PFP monitor is able to effectively detect the execution of a tampered routine that misconfigures the operational mode of a PICDEM Z radio platform affecting the resulting spectral emission In a second experiment our monitor effectively identifies when a transmission routine is modified affecting encryption settings We also present an approach to improve the performance of PFP by characterizing the way a specific platform consumes power This platform characterization which can be done using principal component analysis or linear discriminant analysis allows a PFP monitor to work only on the features that carry the most information As a result the PFP monitor is able to detect execution deviations resulting from a difference of a single bit transition the smallest possible disruptionThe authors would like to thank Wireless Virginia Tech Affiliates for their support This work was supported in part by the National Science Foundation under Grant CNS0910531 Any opinions findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation or Wireless Virginia Tech Affiliates

Keywords:

References

.
Search In Abstract Of Papers:
Other Papers In This Journal:
  1. Wide-locking range ÷3 series-tuned injection-locked frequency divider
  2. Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture
  3. Analytical modeling methodology for ultrawideband low noise amplifiers with generalized filter-based impedance matching
  4. Low-voltage low-power improved linearity CMOS active resistor circuits
  5. Systematic design of analog integrated circuits using ant colony algorithm based on noise optimization
  6. Clock jitter impact on the performance of general charge sampling amplifiers
  7. Design of PR NMDFB based up and down converters for transmit downlink and receive uplink of combined 3GPP LTE and UMTS radios
  8. Automatic tuning of digitally-controllable positive-feedback OTAs in continuous-time sigma–delta modulators
  9. The “Analog Journal” celebrates its 20th Anniversary!
  10. Voltage mode third order quadrature oscillators using OTRAs
  11. Construction of CDBA and CDTA behavioral models and the applications in symbolic circuits analysis
  12. High speed BiCMOS linear driver core for segmented InP Mach-Zehnder modulators
  13. Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA
  14. A 2.4-GHz low power polar transmitter for wireless body area network applications
  15. A 1-mW K-band gate AC-coupled VCO with 0.25 V supply voltage
  16. A technique for improving gain and noise figure of common-gate wideband LNAs
  17. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  18. On the design of feed-forward ΣΔ interface for MEMS based accelerometers
  19. Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC
  20. Implementation of an SDR system using an MPI-based GPU cluster for WiMAX and LTE
  21. A digital processor for full calibration of pipelined ADCs
  22. A wide-range VCO with an automatic frequency, amplitude and gain calibration loop
  23. A digitally-assisted error compensation grouping method for element matching improvement in data converters
  24. Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror
  25. A novel design of local-feedback MOS transconductor using techniques for cancellation of mobility degradation and linearization of differential output current characteristic
  26. A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers
  27. A high speed four-stage operational amplifier in 65 nm CMOS
  28. Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages
  29. A low-cost programmable clock generator for switched-capacitor circuit applications
  30. Quantum-inspired evolutionary algorithm for analog test point selection
  31. A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
  32. An adaptive voltage scaling DC–DC converter based on embedded pulse skip modulation
  33. High-Gain Class-AB OTA with Low Quiescent Current
  34. A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver
  35. A self-powered power conditioning circuit for battery-free energy scavenging applications
  36. Fully integrated 1.2-μA and 13-μA quiescent current LDOs with improved transient response
  37. On the design of active inductors with current-controlled voltage sources
  38. Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic
  39. New RF power amplifiers modeling and identification for wideband applications
  40. Novel detector implementations for 3G LTE downlink and uplink
  41. A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
  42. Comment on “realization of series and parallel R-L and C-D impedances using single differential voltage current conveyor”
  43. A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system
  44. A broad-band V-band power amplifier using a reduced access-resistance transistor layout in 65-nm CMOS
  45. Comparison of high impedance input topologies with low EMI susceptibility
  46. Nonlinear modeling and analysis of a Doherty power amplifier driven by non-constant envelope signals
  47. Hybrid delta-sigma ADC
  48. A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS
  49. Introduction to the Special issue on IEEE-Latin American Symposium on Circuits and Systems
Search Result: