Authors: P Gogna E Suarez M Lingalugari J Chandy E Heller ES Hasaneen FC Jain
Publish Date: 2013/10/08
Volume: 42, Issue: 11, Pages: 3337-3343
Abstract
This paper describes novel multibit static randomaccess memories SRAMs implemented using fourchannel spatial wavefunction switched fieldeffect transistors SWS FETs with Ge quantum wells and ZnSSe barriers A twobit SRAM cell consists of two backtoback connected fourchannel SWS FETs where each SWS FET serves as a quaternary inverter This architecture results in a reduction of the fieldeffect transistor FET count by 75 and data interconnect density by 50 The designed twobit SRAM cell is simulated using Berkeley shortchannel insulatedgate fieldeffect transistor equivalentchannel models for 25nm FETs In addition the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count The concept of spatial wavefunction switching SWS in the FET structure has been verified experimentally for two and fourwell structures Quantum simulations exhibiting SWS in fourwell Ge SWS FET structures using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator are presented These structures offer higher contrast than SiSiGe SWS FETs
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