Authors: H Y Zhang X W Zhang
Publish Date: 2015/03/13
Volume: 44, Issue: 7, Pages: 2396-2405
Abstract
The 25D package with distributed vias on silicon interposer has received great attention due to its potential for heterogeneous integration The overmolded 25D package protects the silicon die and interposer from environmental damage which on the other hand induces undesirable thermal resistance due to low thermal conductivity of the molding compound In this paper a thermally enhanced 25D package with exposed die is proposed fabricated and examined from the thermal enhancement viewpoint The high power thermal test die was first assembled on a silicon interposer with through silicon vias and connected to the substrate which was followed by the overmolding and backgrinding processes to form the partially molded PM package with exposed die for direct heat sink attachments Experiments were conducted to examine the thermal performance under different thermal conditions Under natural convection without thermal enhancement there was no performance difference between the PM package and the overmolded package However when the package top was mounted with a thermally enhanced structure such as a pin fin heat sink the thermal resistance of PM package was significantly reduced The advantage was more prominent with the attachment of a high performance liquid cooling heat sink Thermal simulation models were also constructed to examine the thermal performances under different test conditions and the realistic thermal interface resistance of 05 Kcm2/W was estimated based on the package warpage The computed thermal resistances agreed with measurement resultsPart of work was conducted during the first author’s visit to the Institute of Microelectronics ASTAR The authors thank Dexter Sharon Lim and BL Lau for their help during the course of the work This work is also supported by Shanghai Higher Education Institution under Eastern Scholar Program
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